Delay-locked loop (DLL) operation mode controller circuit and method for controlling thereof
US8890593B1 · kind B1 · utility
2Cited by
4References
16Claims
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Key dates
| Filing date | Mar 12, 2014 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0802
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop (DLL) operation mode control circuit and corresponding method are provided in which one of the output values from a display driver IC (DDI) is detected to switch a DLL block to standby mode. In examples, a CLKP/N frequency and CLKP/N common terminal voltage status are used to switch mode. Accordingly, since inoperable frequency domains otherwise present in a normal mode interval of the DLL block is included into standby mode, more stable operation of the DLL circuit is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.