Dynamic clock phase control architecture for frequency synthesis
US8890595B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | May 16, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | May 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/13
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.