Intrinsic comparator delay for output clamping circuit
US8890599B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Dec 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage. The clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold. A first switch supplies the reference voltage to the comparator. The first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage. A second switch is coupled to the input voltage and a second feedback path in the comparator. The second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.