High noise immunity with latch-up free ESD clamp
US8891215B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Dec 11, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.