Fault tolerant fail-safe link
US8891218B2 · kind B2 · utility
6Cited by
27References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Oct 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure is generally directed to a plurality of solid state switches of varying periphery sizes connected in series between a power source and a load. A built-in test circuit senses an overvoltage condition across one or more of the varying periphery sizes and opens or closes the one or more of the varying periphery sizes in accordance with a measured voltage across at least one solid state switch of the plurality of solid state switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.