Ten-transistor dual-port SRAM with shared bit-line architecture
US8891289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Apr 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The third switch set is connected to a complement second A-port bit line, a complement second B-port bit line, and the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.