50 Gb/s ethernet using serializer/deserializer lanes
US8891561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | May 3, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.