Hardware to support looping code in an image processing system
US8892853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2010 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Aug 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V20/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.