Parasitic component library and method for efficient circuit design and simulation using the same
US8893066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.