Return address optimisation for a dynamic code translator
US8893100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | May 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4552
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.