System and method for partitioning resources in a system-on-chip (SoC)
US8893267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2011 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Oct 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.