Method for manufacturing double-gate structures
US8895398B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | May 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.