Continuous-time oversampling pipeline analog-to-digital converter
US8896475B2 · kind B2 · utility
21Cited by
8References
27Claims
0Family size
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Key dates
| Filing date | Apr 24, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Apr 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.