Data-driven noise reduction technique for analog to digital converters
US8896476B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.