Nonvolatile memory cells and methods of making such cells
US8897067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.