On-chip packet cut-through
US8897316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2010 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.