Power detector with temperature compensation
US8897727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/3036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.