Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached
US8898494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Jun 3, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.