Low latency data transfer between clock domains operated in various synchronization modes

US8898503B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Daniel M. Dreps · Georgetown, US
• Frank D. Ferraiolo · New Windsor, US
• Hubert Harrer · Böblingen, DE
• Pak-kin Mak · Poughkeepsie, US
• Ching-Lung Tong · Highland Mills, US
• Tobias Webel · Eppelheim, DE
• Ulrich Weiss · Holzgerlingen, DE

Key dates

• Filing date: Nov 7, 2013
• Grant date: Nov 25, 2014
• Expiry date: Nov 7, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F1/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.