Handling a failed processor of a multiprocessor information handling system
US8898517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2011 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Aug 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.