Semiconductor wafer, semiconductor device, and method of producing semiconductor wafer

US8901605B2 · kind B2 · utility

Assignee

• National Institute of Advanced Industrial Science and Technology · JP

Inventors

• Tomoyuki Takada · Tokyo, JP
• Sadanori Yamanaka · Tsukuba, JP
• Masao Shimada · Tokyo, JP
• Masahiko Hata · Tsukuba, JP
• Taro Itatani · Tsukuba, JP
• Hiroyuki Ishii · Yokohama, JP
• Eiji Kume · Hachioji, JP

Key dates

• Filing date: Sep 5, 2013
• Grant date: Dec 2, 2014
• Expiry date: Sep 5, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P70/50

Abstract

There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0≦x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.