Trench-gate semiconductor device
US8901638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2009 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Mar 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
A trench-gate semiconductor device is disclosed, in which the player (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The replacement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region. The invention does not require a RESURF device structure, so has wide process windows, since the dopant levels and layer thicknesses do not have to be controlled to provide charge balancing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.