Semiconductor memory device
US8901712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory.A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer.A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.