Placement, rebuffering and routing structure for PLD interface
US8901961B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Nov 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface. The interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debugging circuits, partial reconfiguration circuits, multi-plexing circuits, pipelining circuits and storage circuits. The PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.