Patent · US Active

Phase locked loop and method for operating the same

US8901974B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventors

Puneet Sareen · Delhi, IN
Markus Dietl · Munich, DE
Ketan Dewan · Unterhaching, DE
Edmond F. George · Thrissur, IN

Key dates

Filing date	Jan 30, 2013
Grant date	Dec 2, 2014
Priority date	—
Expiry date	Jan 30, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/06
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.