System and method for high speed data parallelization for an N-phase receiver
US8902091B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Sep 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.