Latching circuits for MEMS display devices
US8902205B2 · kind B2 · utility
5Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | May 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0857
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The described latching circuits can be formed using transistors of a single conductivity type. The transistors can be n-type transistors or p-type transistors. The latching circuits include at least one pre-charge transistor and at least one output terminal discharge transistor. Timing schemes are also described for operating the latching circuits. Pixel circuits and display devices that include these latching circuits are also described. The display devices are formed from an arrangement of the latching circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.