Method of maintaining a memory state
US8902663B1 · kind B1 · utility
60Cited by
347References
20Claims
0Family size
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Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of maintaining a memory state of a 3D memory, wherein the memory includes at least a first cell and a second cell overlying the first cell, the method including: applying a back-bias to the first cell and the second cell without interrupting data access to the memory, and generating at least two stable floating body charge levels of the memory state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.