Semiconductor memory device
US8902664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a control circuit applies a pass potential to a first word line and a preliminary read-out potential to a second word line. The control circuit reads data from a first memory cell transistor at a first condition in a case where a second memory cell transistor has been switched to an ON state and at a second condition in a case where the second memory cell transistor has been switched to an OFF state, by the applying of the preliminary read-out potential. The first condition enables the discrimination of a value of the first memory cell transistor in a case where the first memory cell transistor has a threshold in a relatively low distribution. The second condition enables the discrimination of the value of the first memory cell transistor in a case where the first memory cell transistor has a threshold in a relatively high distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.