Input buffered switching device including bypass logic
US8902899B2 · kind B2 · utility
2Cited by
24References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Apr 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a first packet at an input of a switching device and determining whether to insert first data associated with the first packet into a normal buffer of the input. The determination of whether to insert first data associated with the first packet into the normal buffer includes determining whether the first output identifier matches a second output identifier corresponding to second data in the normal buffer that is associated with a second packet. The first data is inserted into the normal buffer when the first output identifier matches the second output identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.