Noise rejection for built-in self-test with loopback
US8904248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Jan 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.