Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
US8904260B2 · kind B2 · utility
7Cited by
9References
7Claims
0Family size
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Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Feb 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.