Structure for stacked CMOS circuits
US8904322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Mar 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.