Method for packaging a semiconductor structure
US8906748B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Feb 9, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application provides a method and semiconductor packaging structure comprising a conductive substrate having a first surface, a first lateral surface and a second lateral surface adjacent to the first surface. A first electrode line with two ends are provided on the first surface and the first lateral surface, and a second electrode line with two ends are provided on the first surface and a second lateral surface respectively. A semiconductor device is provided on the first surface of the conductive substrate which electrically connected to the first electrode line and the second electrode line, a protective plate with through holes covers the first surface, and a sheathing overlays the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.