Semiconductor structure
US8907395B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2011 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Jun 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
Abstract
A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.