Parasitic lateral PNP transistor and manufacturing method thereof
US8907453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Nov 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.