Three-dimensional semiconductor integrated circuit device and method of fabricating the same
US8907459B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2007 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Sep 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.