Phase locked loop with simultaneous locking to low and high frequency clocks
US8907706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2014 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Apr 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/101
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.