Power clamp for high voltage integrated circuits
US8908341B2 · kind B2 · utility
3Cited by
10References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Jun 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.