Circuit having programmable match determination function, and LUT circuit, MUX circuit and FPGA device with such function and method of data writing
US8908408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | May 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.