Using storage cells to perform computation
US8908465B2 · kind B2 · utility
4Cited by
17References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Apr 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.