Clock rate controller and method thereof and electronic device thereof
US8908719B2 · kind B2 · utility
0Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Feb 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/061
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An exemplary embodiment of the present disclosure illustrates a clock rate control method. Firstly, a usage of a first input first output (FIFO) buffer in an electronic device is detected. Then, whether the usage falls within a first specific interval is determined, wherein the first specific interval has a first upper limit value and a first lower limit value. When the usage is larger than the first upper limit value, a clock rate of the inner device of the electronic device is increased; when the usage is less than the first lower limit value, the clock rate is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.