Low latency SIMD architecture for iterative decoders
US8908814B2 · kind B2 · utility
10Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Dec 23, 2011 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Apr 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6569
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and other embodiments associated with iterative decoders are described. According to one embodiment, an apparatus includes a set of decoders that are configured to receive data to be decoded. The apparatus may also include a controller configured to separately control each decoder to initiate a decoding sequence based on an occurrence of a transition point. The transition point is a global transition that occurs iteratively for the set of decoders and is based on iterations in a decoding sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.