Computer system with coherent interconnection
US8909872B1 · kind B1 · utility
4Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Apr 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.