Block-interleaved and error correction code (ECC)-encoded sub data set (SDS) format
US8910012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system for encoding data includes logic adapted for receiving data having one or more sub data sets, a C1 encoder module adapted for generating a plurality of C1 codewords during C1 ECC encoding of the one or more sub data sets, logic adapted for interleaving the plurality of C1 codewords into C1 codeword interleaves (CWIs), each CWI having a predetermined number of C1 codewords interleaved therein, a C2 encoder module adapted for generating a plurality of C2 codewords during C2 ECC encoding of the one or more sub data sets, wherein each C2 codeword has at most one symbol from each C1 codeword in each CWI, and wherein each C2 codeword has one symbol from at least two different C1 codewords in each CWI, and logic adapted for writing the one or more encoded sub data sets to a storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.