System level tools to support FPGA partial reconfiguration
US8910109B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Aug 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present disclosure provide techniques for enabling a user to efficiently design a programmable logic device (PLD) capable of partial reconfiguration. In some implementations, a processor is configured to run a system level design tool and accepts, as inputs from a user, an identification of at least two personas to be used within a reconfigurable region of the PLD. The design tool defines one or more boundaries of a partial reconfig (PR) domain, the PR domain including a partitioned reconfigurable region of the PLD that is selectably configurable as any of the at least two personas. In some implementations, the PR domain includes at least one IP component configured to safely shut down at least one signal, the at least one signal originating from or directed toward an element of the PLD outside of the PR domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.