Signal processing apparatuses capable of processing initially reproduced packets prior to buffering the initially reproduced packets
US8910233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2009 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Dec 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4385
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.