System and method for manipulating security of integrated circuit layout
US8910303B2 · kind B2 · utility
2Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | May 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for manipulating security of an integrated circuit layout, comprising: rendering a PCell that is created by an original user for a successive user; providing an open access to the PCell; providing a PCell evaluator to execute evaluating steps of: getting license information from the PCell, and checking the PCell license information; and generating a layout of a sub-master by instantiating a super-master of the PCell if the PCell license information is valid, or leave the sub-master empty in a PCell view if the PCell license information is invalid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.