Semiconductor device and structure
US8912052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2012 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Oct 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact is aligned to the first transistors with less than about 40 nm alignment error, a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.