Method for manufacturing semiconductor device and semiconductor device
US8912593B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2013 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Jun 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method includes forming a second stacked body on the planarized interlayer insulating film and on the uppermost stair. The second stacked body includes a second conductive film thicker than the first conductive film and a second insulating film stacked on the second conductive film. The method includes dividing the second stacked body into a select gate on the uppermost stair and a plurality of wall portions in a staircase region below the uppermost stair. The method includes forming a plurality of vias piercing the interlayer insulating film under a region between the wall portions and reaching the first conductive film of each of the stairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.